Vertical Tunneling Transistor Based on Gr-hBN-χ_3Borophene Heterostructure with AA Stack

Document Type : Research Article

Authors

1 Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

2 Sharif University of Technology

3 Department of Electrical Engineering, Arak Branch, Islamic Azad University, Arak, Iran

Abstract

In this paper, the electronic properties of vertical Gr-hBN-χ3 borophene heterostructure (AA stack between Gr and hBN layers), i.e. (Gr-hBN-χ3_AA), have been investigated by density functional theory (DFT). By using the tight-binding (TB) model and least-square fitting for TB and DFT band structures, optimal TB parameters are calculated. By exploiting the nonequilibrium Green function technique (NEGF) and capacitive model, we have investigated the vertical tunneling transistor (VTFET) based on Gr-hBN-χ3_AA. Also, the figure of merit (FOM) of the device, such as the ION/IOFF ratio, subthreshold swing, and intrinsic gate-delay time, have been extracted. We have concluded that decreasing the width of graphene nanoribbon (GNR) improves the switching ratio, subthreshold swing, and gate-delay time. Also, compared to previous work (VTFET based on Gr-hBN-χ3_AB), it is seen that changing the stack between Gr and hBN layers has little effect on the FOM of the device. The gate-delay time of the device is 0.011 ps at room temperature.

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AUT Journal of Electrical Engineering
Volume 57, Issue 3
October 2025
Pages 461-472

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