Two-step Dynamic Foreground Auto-Calibration of Binary Weighted Current Steering DAC

Document Type : Research Article

Authors

Department of Electrical and Electronic Engineering, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran

Abstract

This paper presents a novel and versatile calibration technique designed for application in Binary Weighted Current Steering Digital-to-Analog Converters (DACs). The primary motivation for this work stems from the limited availability of calibration methods that address matching accuracy, despite the widespread adoption of such converters. The proposed technique facilitates automatic calibration of the DAC as required, leveraging two distinct clock signals: a low-frequency clock for calibration and a high-frequency clock for standard operational modes. The calibration process employs a unique and algorithmically-driven calibration block to systematically eliminate transistor mismatch-induced current errors across all current sources. A configurable triple-path scheme is implemented to steer previously calibrated least significant bit (LSB) currents into the summing node, which subsequently updates the reference current. This updated reference is then used to calibrate the next most significant bit (MSB) current. To validate the effectiveness of the proposed technique, simulations were conducted for a 10-bit DAC using Cadence tools with TSMC 180nm CMOS technology. The DAC was subjected to an intentionally introduced current error of up to 125 LSB in the binary-weighted current blocks. The simulation, performed at a sampling frequency of 125 MHz with a 1.8 V supply voltage and a 500 nA LSB current, demonstrated the robustness and accuracy of the proposed calibration method.

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References

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AUT Journal of Electrical Engineering
Volume 57, Issue 3
2025
Pages 445-460

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