A CMOS 3.5 GHz Bandwidth Low Noise Amplifier using Active Inductor

Articles in Press

Document Type : Research Article

Authors

1 Assistant Professor, faculty of Technology and Engineering, Shahrekord University, Shahrekord, Iran

2 Ph.D Student, School of Microelectronic, Tianjin University, Tianjin, China

Abstract

This paper presents a 3.5 GHz bandwidth wideband low noise amplifier (LNA) with low power consumption, high power gain, and acceptable linearity in 130 nm CMOS technology. The LNA includes two branches in parallel: a gm-boosted common-gate (CG) path and common-source (CS) current reuse path. The CG path is responsible for providing wideband input impedance matching, while the CS path is used to achieve enough power gain and enhance linearity. The noise cancellation technique is adopted to reduce the noise generated by the gm-boosted CG stage and at the same time, the linearity is taken care of by choosing suitable gain values for CG, CS. Also, an active inductive shunt-peaking technique is used to increase the bandwidth to 3.5 GHz. The post-layout simulation results of the circuit in 130 nm CMOS technology show that in the whole bandwidth of 0.25 GHz to 3.75 GHz the power gain, noise figure, and third-order input intercept point (IIP3) are 15±1 dB, 2.25±0.3 dB, and -5.5 dBm, respectively. Also, the S11 and S22 are less than -15 dB and -19 dB. The proposed LNA consumes 4.7 mW with a 1 V power supply and occupies an area of 0.047 mm2.

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AUT Journal of Electrical Engineering

Articles in Press, Accepted Manuscript
Available Online from 12 January 2025

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