Design and Simulation of Pseudo Ternary Adder based on CNTFET

Document Type : Research Article


Department of Electrical Engineering, Faculty of Engineering, Azarbaijan Shahid Madani University, Tabriz, Iran


Utilizing multiple logic instead of binary logic levels makes the same system to be realized with reduced number of internal connections and wiring, occupying smaller chip area while achieving higher operational speed. Due to the unique features nanotubes carbon tubes field effect transistors, as well as the possibility of designing different threshold voltages for transistors, designing multi-level logic systems is much simpler and less costly. Therefore, considering that the existing processing systems work on a dual basis, the design of binary to ternary converters and vice versa is very important and basic processing systems. In spite of all advantages mentioned, the multilevel logic systems relay on voltage dividing mechanism to provide suitable mid-voltage outputs. This, however, requires a direct current flow from supply voltage to the ground making the structure power hungry. Eliminating the mid-voltage outputs can help the structure to resemble binary design approach and be more power efficient as discussed in this paper. In this paper, pseudo ternary addition blocks, namely a half-adder, a full-adder block are designed and implemented based on CNTFET which try to eliminate '1' output for mid-stages wherever possible. The proposed adders are implemented, simulated and verified in HSPICE software using 32nm CNTFET technology. The simulation results reveal the proposed pseudo ternary full-adder block consumes just 1.037 μW power and has the propagation delay of 290 ps.


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