This article discusses a multi-stage transimpedance amplifier (known as TIA), which is based on three stages of a modified inverter structure. The traditional inverter structures’ performances are improved adding two cascoded transistors. This new structure benefits from elimination of the Miller-capacitances in comparison with the traditional inverters, which can provide higher speed and wider frequency bandwidth. Manipulating the trade-offs among bandwidth, gain and power consumption beside using Gm/ID technique, this paper introduces a low-power transimpedance amplifier for high-bit rates in optical communication receiver systems. Moreover, active types of inductors are also used to lesson the occupied area and increase the frequency bandwidth. Transferring poles of the improved circuit to higher frequencies means less required DC current for a fixed bandwidth range, which results in low-power characteristic. The proposed circuit is simulated using 90nm CMOS technology parameters. Results for frequency response show the transimpedance gain of 42.3 dBΩ and the bandwidth of 3.47 GHz. Moreover, the circuit consumes 2.7mW using 1V supply, which is relatively close to the targeted 2.5mW power, using gm/ID. Other required simulations such as eye diagram, Monte Carlo, temperature and VDD variations, post layout simulation beside its mathematical equations are also added to manuscript to justify ts performance.