Single-ended 6T SRAM Cell with Low Power/Energy Consumption and High Stability

Document Type : Research Article

Authors

Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

Abstract

In this paper, we propose 6T cell with single-ended characteristics to achieve an improved stability, decrease energy consumption, and decrease leakage power. The cell is compared with strong 10 and 12 transistor structures with good and excellent specifications. However, the above structure is designed to have the best parameters with low size and a minimum number of transistors that reduce the size of the cell. In some parameters, such as the write noise margin, the structure has the best merits in comparison with other structures, even higher than the structures of 12 and 10 transistors. The write operation is enhanced by cutting the pull-down path to the storage node to be written as “1”; the read operation is performed without cutting the pull-down path. At VDD=0.4V, the static power, read margin, write margin, read energy, and write energy of the proposed structure are superior by 33%, 50%, 215%, 9%, and 5%, respectively, in contrast to the traditional 6T. The Electrical Quality Metric (EQM) parameter has been improved about ten times compared with the standard 6T structure, showing that the value of the new structure has been introduced. A Monte Carlo simulation of 5,000 read and write yields in the 32nm technology revealed that our cell has a 2x and 3.4x higher yield than the typical 6T cell. Consequently, the proposed 6T cell is an appropriate option for applications requiring low energy and high robustness.

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References

[1] G.P. Gupta Anu, Asati Abhijit, Novel low-power and stable SRAM cells for sub-threshold operation at 45 nm, International Journal of Electronics, 105(8) (2018) 1399-1415.
[2] S. Naghizadeh, M. Gholami, Two novel ultra-low-power SRAM cells with separate read and write path, Circuits, Systems, and Signal Processing, 38(1) (2019) 287-303.
[3] S. Ahmad, N. Alam, M. Hasan, Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications, AEU-International Journal of Electronics and Communications, 83 (2018) 366-375.
[4] S. Dasgupta, Compact analytical model to extract write Static Noise Margin (WSNM) for SRAM cell at 45-nm and 65-nm nodes, IEEE Transactions on Semiconductor Manufacturing, 31(1) (2017) 136-143.
[5] J. Rabaey, Low power design essentials, Springer Science & Business Media, 2009.
[6] K. Mehrabi, B. Ebrahimi, A. Afzali-Kusha, A robust and low power 7T SRAM cell design, in:  2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS), IEEE, 2015, pp. 1-6.
[7] S. Gupta, K. Gupta, B.H. Calhoun, N. Pandey, Low-power near-threshold 10T SRAM bit cells with enhanced data-independent read port leakage for array augmentation in 32-nm CMOS, IEEE Transactions on Circuits and Systems I: Regular Papers, 66(3) (2018) 978-988.
[8] L. Wen, Y. Zhang, X. Zeng, Column-selection-enabled 10T SRAM utilizing shared diff-VDD write and dropped-VDD read for power reduction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(6) (2019) 1470-1474.
[9] M. Moghaddam, S. Timarchi, M.H. Moaiyeri, M. Eshghi, An ultra-low-power 9T SRAM cell based on threshold voltage techniques, Circuits, Systems, and Signal Processing, 35(5) (2016) 1437-1455.
[10] S. Gupta, K. Gupta, N. Pandey, A 32-nm subthreshold 7T SRAM bit cell with read assist, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(12) (2017) 3473-3483.
[11] C. Kushwah, S.K. Vishvakarma, A single-ended with dynamic feedback control 8T subthreshold SRAM cell, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(1) (2015) 373-377.
[12] M. Nabavi, M. Sachdev, A 290-mV, 3.34-MHz, 6T SRAM with pMOS access transistors and boosted Wordline in 65-nm CMOS technology, IEEE Journal of Solid-State Circuits, 53(2) (2017) 656-667.
[13] J.P. Kulkarni, K. Kim, K. Roy, A 160 mV robust Schmitt trigger based subthreshold SRAM, IEEE Journal of Solid-State Circuits, 42(10) (2007) 2303-2313.
[14] G. Pasandi, S.M. Fakhraie, An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs, IEEE Transactions on electron devices, 61(7) (2014) 2357-2363.
[15] S. Ahmad, Gupta, Mohit Kumar, Alam, Naushad, M. Hasan, Low leakage single Bitline 9 t (sb9t) Static Random Access Memory, Microelectronics Journal, 62 (2017) 1-11.
[16] J. Kim, P. Mazumder, A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS, Integration, 57 (2017) 1-10.
[17] E. Shakouri, B. Ebrahimi, N. Eslami, M. Chahardori, Single-Ended 10T SRAM Cell with High Yield and Low Standby Power, Circuits, Systems, and Signal Processing,  (2021) 1-21.
[18] D. Ingerly, A. Agrawal, R. Ascazubi, A. Blattner, M. Buehler, V. Chikarmane, B. Choudhury, F. Cinnor, C. Ege, C. Ganpule, Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing, in:  2012 IEEE International Interconnect Technology Conference, IEEE, 2012, pp. 1-3.
[19] S. Ahmad, B. Iqbal, N. Alam, M. Hasan, Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis, IEEE Transactions on Device and Materials Reliability, 18(3) (2018) 337-349.
[20] M.R. Kumar, P. Sridevi, Design of an enhanced write stability, high-performance, low power 11T SRAM cell, INTERNATIONAL JOURNAL OF ELECTRONICS, 108(10) (2021) 1652-1675.
[21] D. Nayak, D.P. Acharya, P.K. Rout, U. Nanda, A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate, Microelectronics Journal, 73 (2018) 43-51.
[22] Y. He, J. Zhang, X. Wu, X. Si, S. Zhen, B. Zhang, A half-select disturb-free 11T SRAM cell with built-in write/read-assist scheme for ultralow-voltage operations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(10) (2019) 2344-2353.
[23] S. Gupta, K. Gupta, N. Pandey, Pentavariate Vmin Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read, IEEE Transactions on Circuits and Systems I: Regular Papers, 65(10) (2018) 3326-3337.
[24] G. Torrens, B. Alorda, C. Carmona, D. Malagon-Perianez, J. Segura, S. Bota, A 65-nm reliable 6T CMOS SRAM cell with minimum size transistors, IEEE Transactions on Emerging Topics in Computing, 7(3) (2017) 447-455.
[25] A. Yadav, S. Nakhate, Low standby leakage 12T SRAM cell characterisation, International Journal of Electronics, 103(9) (2016) 1446-1459.
[26] J. Guo, L. Zhu, W. Liu, H. Huang, S. Liu, T. Wang, L. Xiao, Z. Mao, Novel radiation-hardened-by-design (RHBD) 12T memory cell for aerospace applications in nanoscale CMOS technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(5) (2017) 1593-1600.
[27] C.-C. Wang, D.-S. Wang, C.-H. Liao, S.-Y. Chen, A leakage compensation design for low supply voltage SRAM, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(5) (2015) 1761-1769.
[28] K.C. Chun, P. Jain, J.H. Lee, C.H. Kim, A 3T gain cell embedded DRAM utilizing preferential boosting for high density and low power on-die caches, IEEE Journal of Solid-State Circuits, 46(6) (2011) 1495-1505.
[29] G. Pasandi, M. Pedram, Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in SRAMs, IET Circuits, Devices & Systems, 12(4) (2018) 460-466.
[30] H. Jiao, Y. Qiu, V. Kursun, Low power and robust memory circuits with asymmetrical ground gating, microelectronics journal, 48 (2016) 109-119.
AUT Journal of Electrical Engineering
Volume 54, Issue 2 (Special Issue)
December 2022
Pages 343-360

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