Analysis and Design of High Gain, and Low Power CMOS Distributed Amplifier Utilizing a Novel Gain-cell Based on Combining Inductively Peaking and Regulated Cascode Concepts

Document Type : Research Article



In this study an ultra-broad band, low-power, and high-gain CMOS Distributed Amplifier (CMOS-DA)
utilizing a new gain-cell based on the inductively peaking cascaded structure is presented. It is created by
cascading of inductively coupled common-source (CS) stage and Regulated Cascode Configuration (RGC).
The proposed three-stage DA is simulated in 0.13 μm CMOS process. It achieves flat and high  
 of 26.5 ±
0.4 dB over the frequencies range from DC up to 13 GHz 3-dB bandwidth, and it dissipates only 9.95 mW.
The IIP3 is simulated and achieved -10 dBm at 6 GHz. Also, simulated input referred 1-dB compression
point at 6 GHz achieves the value of -20 dBm. Both input and output matches are better than -11 dB. To
obtain the low power and high gain requirements, the advantages of the bulk terminal are exploited in the
proposed CMOS-DA. It adopts the method of forward body biasing in output MOS transistor to achieve
higher transconductance and lower power consumption. Additionally, the Monte Carlo (MC) simulation is
performed to take into account the risks associated with various input parameters which they receive little or
no consideration in simulating of designs utilizing ideal components. MC simulation predicts an estimate of
the good accuracy performance of the proposed design under various conditions.


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