Studying the impact of technology scaling on the performance of MOSFET devices using semi-empirical modeling through the inversion coefficient

Document Type : Research Article

Authors

1 PhD candidate, Electrical Engineering, Shahid Beheshti university, Tehran, Iran

2 Associate professor, Electrical Engineering, Shahid Beheshti university, Tehran, Iran

Abstract

For six decades, integrated circuit design and manufacturing have fueled information technology's explosive growth, powering modern computing and advancing contemporary civilization. Advancements in this industry are primarily driven by the shrinking of technology and the reduction of transistor channel length in metal oxide semiconductor devices. This paper examines the impact of these factors on the characteristics and performance trade-offs of metal oxide semiconductor devices, focusing on the inversion coefficient as a key design parameter across all inversion regions (Weak Inversion, Moderate Inversion, and Strong Inversion). The performance trade-offs, analyzed in terms of inversion coefficient in 90nm and 180nm processes, encompass sizing relationships, DC bias and small signal parameters, gain and bandwidth, gate-referred thermal and flicker noise, DC mismatch, gate-source leakage and figure of merit for low-power radio frequency designs. Graphically displaying performance trends against inversion coefficient across two fabrication technologies allows for selection of desired trade-offs as the process is shrunk. Finally, an operating plane for metal oxide semiconductor devices is presented, enabling selection of appropriate bias points to optimize device performance within the desired circuit as technology scales down.

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AUT Journal of Electrical Engineering
Volume 57, Issue 3
October 2025
Pages 473-484

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