Advances on CMOS Folded-Cascode Operational Transconductance

Document Type : Review Article

Author

Integrated Circuits Design Laboratory, Department of Electrical Engineering, Amirkabir University of Technology (Tehran Polytechnic), Tehran, Iran

Abstract

In this paper, a tutorial review on several structural improvements of the CMOS folded-cascode Operational Transconductance Amplifier (OTA) is presented. After a brief discussion on the structure and operation of the conventional Folded-Cascode Amplifier, its several architectural improvements are reviewed. These improvements include advances on class A and class AB Folded-Cascode Amplifier s and recycling Folded-Cascode Amplifier. Afterwards, several improved class A and class AB recycling folded-cascode Operational Transconductance Amplifiers are discussed, and finally some two-stage Operational Transconductance Amplifiers based on the current recycling technique are reviewed. As it can be seen, many architectural innovations have been proposed to improve both small-signal parameters, including DC gain, unity-gain bandwidth, phase margin, and large-signal operation, which is usually characterized by slew rate in the proposed OTAs compared to the basic Folded-Cascode Amplifier. Current recycling, shunt current sources, cross-coupled transistors to realize local positive feedback paths, local Common-Mode Feedback, Flipped Voltage Follower cells to realize class AB operation, active current mirrors, and several other techniques have been utilized in the structural improvements of the basic folded-cascode Operational Transconductance Amplifier. The achieved results are more promising and demonstrate substantial achievements in the design of Operational Transconductance Amplifiers in low-voltage and more scaled nano-meter CMOS processes.

Keywords

Main Subjects

References

  1. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Second Edition, 2012.
  2. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, Second Edition, 2016.
  3. Yavari and O. Shoaei, “Low-Voltage Low-Power Fast-Settling CMOS Operational Transconductance Amplifiers for Switched-Capacitor Applications,” IEE Proceedings on Circuits, Devices, and Systems, vol. 151, no. 6, pp. 573-578, Dec. 2004.
  4. Yavari, “Hybrid Cascode Compensation for Two-Stage CMOS Opamps,” IEICE Transactions on Electronics, Special Section on Analog Circuit and Device Technologies, vol. E88-C, no. 6, pp. 1161-1165, Jun. 2005.
  5. Yavari, “Active-Feedback Single Miller Capacitor Frequency Compensation Techniques for Three-Stage Amplifiers,” Journal of Circuits, Systems, and Computers, World Scientific, vol. 19, no. 7, pp. 1381-1398, Nov. 2010.
  6. Mojarad and M. Yavari, “A Low Power Four-Stage Amplifier for Driving Large Capacitive Loads,” International Journal of Circuit Theory and Applications, vol. 42, no. 9, pp. 978-988, Sept. 2014.
  7. Golabi and M. Yavari, “High-Speed Three-Stage Operational Transconductance Amplifiers for Switched-Capacitor Circuits,” Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 413-417, May 2014.
  8. Golabi and M. Yavari, “A Three-Stage Class AB Operational Amplifier with Enhanced Slew Rate for Switched-Capacitor Circuits,” Analog Integrated Circuits and Signal Processing, vol. 83, no. 1, pp. 111-118, Apr. 2015.
  9. Alizadeh Arand and M. Yavari, “A Three-Stage NMC Operational Amplifier with Enhanced Slew Rate for Switched-Capacitor Circuits,” Analog Integrated Circuits and Signal Processing, vol. 106, no. 3, pp. 697-706, Mar. 2021.
  10. A. Mohammed and G. W. Roberts, “Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 68, no. 12, pp. 4993-5006, Dec. 2021.
  11. Yavari, N. Maghari, and O. Shoaei, “An Accurate Analysis of Slew-Rate for Two-Stage CMOS Opamps,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 52, no. 3, pp. 164-167, Mar. 2005.
  12. Yavari, O. Shoaei, and A. Rodriguez-Vazquez, “Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation,” Design Automation and Test in Europe, DATE, Munich, Germany, pp. 144-149, March 2006.
  13. Yavari, “A Design Procedure for CMOS Three-Stage NMC Amplifiers,” IEICE Trans. Fundamentals, vol. E94-A, no. 2, pp. 639-645, Feb. 2011.
  14. Golabi and M. Yavari, “Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits,” Analog Integrated Circuits and Signal Processing, Springer, vol. 80, no. 2, pp. 195-208, Aug. 2014.
  15. -H. Lin, C.-K. Wu, and M.-C. Tsai, “A 0.8-V 0.25-mW current-mirror OTA with 160-MHz GBW in 0.18-mm CMOS,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 54, no. 2, pp. 131–135, Feb. 2007.
  16. Ali, “A power efficient gain enhancing technique for current mirror Operational Transconductance Amplifiers,” Microelectronics Journal, vol. 46, no. 2, pp. 183-190, Feb. 2015.
  17. Póvoa, N. Lourenço, R. Martins, A. Canelas, N. Horta , and J. Goes, “Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 65, no. 11, pp. 1599-1603, Nov. 2018.
  18. Póvoa, N. Lourenço, R. Martins, A. Canelas, N. Horta , and J. Goes, “A Folded Voltage Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 67, no. 2, pp. 230-234, Feb. 2020.
  19. Nakamura and L. R. Carley, “An enhanced fully differential folded-cascode op amp,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 563-568, Apr. 1992.
  20. Olivera-Romero and J. Silva-Martinez, “A folded-cascode OTA based on complementary differential pairs for HF applications,” Design of Mixed-Mode Integrated Circuits Design and Applications, pp. 57–60, Jul. 1999.
  21. Roewer and U. Kleine, “A Novel Class of Complementary Folded-Cascode Opamps for Low Voltage,” IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1080-1083, Aug. 2002.
  22. Adut, J. Silva-Martinez, and M. Rocha-Perez, “A 10.7-MHz sixth-order SC ladder filter in 0.35-mm CMOS technology,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 8, pp. 1625–1635, Aug. 2006.
  23. Yavari and O. Shoaei, “A Novel Fully-Differential Class AB Folded-Cascode OTA,” IEICE Electron. Express, vol. 1, no. 13, pp. 358-362, Oct. 2004.
  24. Yavari and O. Shoaei, “A Novel Fully-Differential Class AB Folded-Cascode OTA for Switched- Capacitor Applications,” IEEE International Conference on Electronics, Circuits and Systems, ICECS, 2005.
  25. G. Carvajal, J. Ramirez-Angulo, A. J. Lopez-Martin, A. Torralba, J. A. G. Galan, A. Carlosena, and F.M. Chavero, “The Flipped Voltage Follower: a useful cell for low-voltage low-power circuit design”, IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 7, pp. 1276-1291, Jul. 2005.
  26. Roh, “High-gain class AB OTA with low quiescent current,” Analog Integrated Circuits and Signal Processing, vol. 47, no. 2, pp. 225-228, May 2006.
  27. Yavari, “A New Class AB Folded-Cascode Operational Amplifier,” IEICE Electron. Express, vol. 6, no. 7, pp. 395-402, Apr. 2009.
  28. J. Lopez-Martin, M. Pilar Garde, J. M. Algueta, C. A. de la Cruz Blas, R. G. Carvajal, and J. Ramirez-Angulo, “Enhanced Single-Stage Folded Cascode OTA Suitable for Large Capacitive Loads,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 65, no. 4, pp. 441-445, Apr. 2018.
  29. Akbari, O. Hashemipour, and F. Moradi, “A High Slew Rate CMOS OTA with Dynamic Current Boosting Paths,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
  30. Beloso-Legarra, C. A. de la Cruz-Blas, A. J. Lopez-Martin, and J. Ramirez-Angulo, “Gain-Boosted Super Class AB OTAs Based on Nested Local Feedback,” IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 68, no. 9, pp. 3562-3573, Sept. 2021.
  31. Centurelli, , P. Monsurrò, G. Parisi, P. Tommasino, and A. Trifiletti, “A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 65, no. 11, pp. 1504-1508, Nov. 2018.
  32. Assaad and J. Silva-Martinez, “Enhancing general performance of folded cascode amplifier by recycling current,” IET Electronics Letters, vol. 43, no. 23, 8th Nov. 2007.
  33. Assaad and J. Silva-Martinez, “The recycling folded-cascode: a general enhancement of the Folded-Cascode Amplifier,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2535-2542, Sept. 2009.
  34. Assaad and J. Silva-Martinez, “Recent Advances on the Design of High-Gain Wideband
    Operational Transconductance Amplifiers,” VLSI Design, pp. 1-11, 2009.
  35. Nagulapalli, K. Hayatleh, S. Barker, S. Zourob, and N. Yassine, “An OTA gain enhancement technique for low power biomedical applications,” Analog Integrated Circuits and Signal Processing, vol. 95, no. 6, pp. 387-394, Jun. 2018.
  36. Mohtashamnia and M. Yavari, “A Low-Power Low-Noise Neural Recording Amplifier with an Improved Recycling Telescopic-Cascode OTA,” International Journal of Electronics and Communications, vol. 154, no. 9, pp. 1-11, 154312, Sept. 2022; Published online: Jul. 08, 2022.
  37. -L. Li, K.-F. Han, X. Tan, N. Yan, and H. Min, “Transconductance enhancement method for Operational Transconductance Amplifiers,” IET Electronics Letters, vol. 46, no. 19, 16th Sept. 2010.
  38. Zhao, H. Fang, and J. Xu, “DC gain enhancement method for recycling folded cascode amplifier in deep submicron CMOS technology,” IEICE Electron. Express, vol. 8, no. 17, pp. 1450-1454, Sept. 2011.
  39. Yan, P.-I. Mak, and R. P. Martins, “Double recycling technique for folded-cascode OTA,” Analog Integrated Circuits and Signal Processing, vol. 71, no. 4, pp. 137-141, Apr. 2012.
  40. Akbari, “Single-stage fully recycling folded cascode OTA for switched-capacitor circuits,” Electronics Letters, vol. 51, no. 13, pp. 977-979, 25th Jun. 2015.
  41. Aghaee, S. Biabanifard, and A. Golmakani, “Gain boosting of recycling folded cascode OTA using positive feedback and introducing new input path,” Analog Integrated Circuits and Signal Processing, vol. 47, no. 2, pp. 225-228, May 2016.
  42. D. Sundararajan and S. M. Rezaul Hasan, “Quadruply Split Cross-Driven Doubly Recycled gm-Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 63, no. 6, pp. 543-547, Jun. 2016.
  43. Zhao, H. Fang, and J. Hu, “A transconductance enhanced recycling structure for Folded-Cascode Amplifier,” Analog Integrated Circuits and Signal Processing, vol. 71, no. 1 pp. 259-263, Jul. 2012.
  44. Zhao, H. Fang, and J. Xu, “Phase-margin enhancement technique for recycling folded cascode amplifier,” Analog Integrated Circuits and Signal Processing, vol. 74, no. 2, pp. 479-483, Feb. 2013.
  45. Zhang, M. Deng, and Q. Zhang, “A high DC-gain low-power current recycling amplifier in deep sub-micron CMOS technology,” IEICE Electron. Express, vol. 10, no. 19, pp. 1-7, Oct. 2013.
  46. Zhao, H. Fang, and J. Xu, “A power-efficient improved recycling folded cascode amplifier,” International Journal of Electronics, vol. 100, no. 12, pp. 1660-1666, Dec. 2013.
  47. Zhao, H. Fang, and J. Xu, “A Low Power Current Recycling Constant-Gm Rail-To-Rail OTA,” Journal of Circuits, Systems, and Computers, vol. 23, no. 2, pp. 1-12, Feb. 2014.
  48. -I. Mak, M. Liu, Y. Zhao, and R. P. Martins, “Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability,” International Journal of Circuit Theory and Applications, vol. 42, no. 6, pp. 605-619, Jun. 2014.
  49. Yavari and T. Moosazadeh, “A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits,” Analog Integrated Circuits and Signal Processing, Springer, vol. 79, no. 3, pp. 589-598, Jun. 2014.
  50. Sonmez, H. Kulah, and T. Akın, “A SD micro accelerometer with 6 mg/ÖHz resolution and 130 dB
    dynamic range,” Analog Integrated Circuits and Signal Processing, vol. 81, no. 11, pp. 471-485, Nov. 2014.
  51. Akbari, S. Biabanifard, S. Asadi, M. C. E. Yagoub, “High performance folded cascode OTA using positive feedback and recycling structure,” Analog Integrated Circuits and Signal Processing, vol. 82, no. 1, pp. 217-227, Jan. 2015.
  52. Ahmed, E. Shah, F. Tang, and A. Bermak, “An Improved Recycling Folded Cascode Amplifier with Gain Boosting and Phase Margin Enhancement,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2473-2476, May 2015.
  53. Zhao, Q. Zhang, Y. Wang, and M. Deng, “Transconductance and slew rate improvement technique for current recycling folded cascode amplifier,” International Journal of Electronics and Communications, vol. 70, no. 3, pp. 326-330, Mar. 2016.
  54. Akbari, A. Hassanzadeh, and O. Hashemipour, “Slew rate boosting technique for an upgraded transconductance amplifier,” Analog Integrated Circuits and Signal Processing, vol. 88, no. 7, pp. 57-63, Jul. 2016.
  55. V. Feizbakhsh, G. Yosefi, “An enhanced fast slew rate recycling folded cascode Op-Amp with general improvement in 180 nm CMOS process,” International Journal of Electronics and Communications, vol. 101, no. 3, pp. 200-217, Mar. 2019.
  56. Hou, B. Zhou, X. Li, Z. Gao, Qi Wei, and R. Zhang, “An Analog Interface Circuit for Capacitive Angle Encoder Based on a Capacitance Elimination Array and Synchronous Switch Demodulation Method,” MDPI Sensors, vol. 19, pp. 1-12, Jul. 2019.
  57. S. Khade, V. Vyas, and M. Sutaone, “A technique to enhance the transconductance of micro-power improved recycling folded cascode Operational Transconductance Amplifier with reasonable phase margin,” International Journal of Electronics and Communications, vol. 108, no. 8, pp. 148-157, Aug. 2019.
  58. Wang, Q. Zhang, S. S. Lu, X. Zhao, H. Trinh, and P. Shi, “A Robust Local Positive Feedback Based Performance Enhancement Strategy for Non-Recycling Folded Cascode OTA,” IEEE Transactions on Circuits and Systems—I: Regular Papers, vol. 67, no. 9, pp. 2897-2908, Sept. 2020.
  59. Ghaemnia and O. Hashemipour, “An ultra-low power high gain CMOS OTA for biomedical applications,” Analog Integrated Circuits and Signal Processing, vol. 99, no. 6, pp. 529-537, Jun. 2019.
  60. Yavari, “Single-stage class AB operational amplifier for SC circuits,” IET Electronics Letters, vol. 46, no.14, pp. 977-979, 8th July 2010.
  61. Zhao, Y. Wang, D. Jia, and L. Dong, “Ultra-high current efficiency single-stage class-AB OTA with completely symmetric slew rate,” International Journal of Electronics and Communications, vol. 87, no. 4, pp. 65-69, Apr. 2018.
  62. Zhao, Y. Wang, and L. Dong, “Super current recycling folded cascode amplifier with ultra-high current efficiency,” Integration, the VLSI Journal, vol. 62, no. 6, pp. 322-328, Jun. 2018.
  63. Pilar Garde, A. Lopez-Martin, R. Gonzalez Carvajal, and J. Ramirez-Angulo, “Super Class-AB Recycling Folded Cascode OTA,” IEEE J. Solid-State Circuits, vol. 53, no. 9, pp. 2614-2623, Sept. 2018.
  64. M. Algueta-Miguel, A. Lopez-Martin, M. Pilar Garde, C. A. De la Cruz, and J. Ramirez-Angulo, “±0.5 V 15 μW Recycling Folded Cascode Amplifier With 34767 MHz·pF/mA FOM,” IEEE Solid-State Circuits Letters, vol. 1, no. 7, pp. 170-173, Jul. 2018.
  65. Lopez-Martin, M. Pilar Garde, J. M. Algueta-Miguel, J. Beloso-Legarra, R. G. Carvajal, and J. Ramirez-Angulo, “Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques,” Applied Sciences, vol. 11, pp. 1-19, Apr. 2021.
  66. Lv, X. Zhao, Y. Wang, L. Dong, Y. Xin, and L. Yu, “A low-power second-order sigma-delta modulator for MEMS digital geophones,” International Journal of Electronics and Communications, vol. 119, no. 5, pp. 1-9, May 2020.
  67. Zhang, Y. Wang, X. Zhao, and L. Dong, “Single-stage multipath class-AB bulk-driven OTA with enhanced power efficiency,” International Journal of Electronics and Communications, vol. 107, no. 7, pp. 39-48, Jul. 2019.
  68. Deo, T. Sharan and T. Dubey, “Subthreshold biased enhanced bulk-driven double recycling current
    mirror OTA,” Analog Integrated Circuits and Signal Processing, vol. 105, no. 11, pp. 229-242, Nov. 2020.
  69. Wen, Q. Zhang, X. Zhao, X. Lv, and Y. Wang, “Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology,” Integration, the VLSI Journal, vol. 68, no. 9, pp. 62-70, Sept. 2019.
  70. -Y. Kuo and S.-D. Tsai, “An Enhanced Scheme of Multi-Stage Amplifier With High-Speed High-Gain Blocks and Recycling Frequency Cascode Circuitry to Improve Gain-Bandwidth and Slew Rate,” IEEE Access, vol. 7, pp. 130820-131829, Sept. 2019.
  71. Xin, X. Zhao, B. Wen, L. Dong, and X. Lv, “A High Current Efficiency Two-Stage Amplifier With Inner Feedforward Path Compensation Technique,” IEEE Access, vol. 8, pp. 22664-22671, Feb. 2020.
  72. M. Anisheh, H. Abbasizadeh, H. Shamsi, C. Dadkhah, and K.-Y. Lee, “98-dB Gain Class-AB OTA With 100 pF Load Capacitor in 180-nm Digital CMOS Process,” IEEE Access, vol. 7, pp. 17772-17779, Feb. 2019.
  73. Banagozar and M. Yargholi, “Ultra-low power two-stage class-AB recycling double folded cascode OTA,” International Journal of Electronics and Communications, vol. 110, no. 10, pp. 1-12, Oct. 2019.
  74. Yen and B. J. Blalock, “A High Slew Rate, Low Power, Compact Operational Amplifier Based on the Super-Class AB Recycling Folded Cascode,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 9-12, Aug. 2020.
  75. Park, Y. A. Tavares, J. Lee, J. Wo, and M. Lee, “5th-Order Continuous-Time Low-Pass Filter Achieving 56 MHz Bandwidth 30.5 dBm IIP3 With a Novel Low-Distortion Amplifier,” IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 68, no. 6, pp. 1768-1772, Jun. 2021.
AUT Journal of Electrical Engineering
Volume 54, Issue 2 (Special Issue)
December 2022
Pages 315-332

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