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<Article>
<Journal>
				<PublisherName>Amirkabir University of Technology</PublisherName>
				<JournalTitle>AUT Journal of Electrical Engineering</JournalTitle>
				<Issn>2588-2910</Issn>
				<Volume>56</Volume>
				<Issue>3</Issue>
				<PubDate PubStatus="epublish">
					<Year>2024</Year>
					<Month>07</Month>
					<Day>01</Day>
				</PubDate>
			</Journal>
<ArticleTitle>Low-Power MOSFET-Only Subthreshold Voltage Reference with High PSRR</ArticleTitle>
<VernacularTitle></VernacularTitle>
			<FirstPage>439</FirstPage>
			<LastPage>452</LastPage>
			<ELocationID EIdType="pii">5446</ELocationID>
			
<ELocationID EIdType="doi">10.22060/eej.2024.23046.5583</ELocationID>
			
			<Language>EN</Language>
<AuthorList>
<Author>
					<FirstName>Mohammad</FirstName>
					<LastName>Rashtian</LastName>
<Affiliation>Department of Aviation Electronics, Civil Aviation Technology College, Tehran, Iran</Affiliation>

</Author>
<Author>
					<FirstName>Mahdi</FirstName>
					<LastName>Shahpasandi</LastName>
<Affiliation>Department of Aviation Electronics, Civil Aviation Technology College, Tehran, Iran</Affiliation>

</Author>
</AuthorList>
				<PublicationType>Journal Article</PublicationType>
			<History>
				<PubDate PubStatus="received">
					<Year>2024</Year>
					<Month>03</Month>
					<Day>09</Day>
				</PubDate>
			</History>
		<Abstract>This work presents a sub-nanowatt voltage reference (VR) achieving a high-power supply ripple rejection (PSRR). It utilizes a self-current biasing circuit to reduce the voltage dependency of the output voltage (V&lt;sub&gt;REF&lt;/sub&gt;) to the power supply variations. For low-power operation, all transistors operate in the subthreshold region. The design&#039;s performance is verified through post-layout and Monte Carlo simulations in a standard 180 nm CMOS process. Results show that the proposed bandgap achieves an output voltage of 0.150 V with a PSRR of -81.5 dB at V­­&lt;sub&gt;dd&lt;/sub&gt; = 1V. Notably, it eliminates the need for an additional startup circuit and consumes only 0.72 nW at T = 27°C with V&lt;sub&gt;dd&lt;/sub&gt; = 0.5V. The proposed voltage reference exhibits a temperature coefficient (TC) of approximately 18 ppm/°C over a temperature range of -20°C to 130°C while without using a trimming circuit a reasonable (σ &lt;sub&gt;VREF&lt;/sub&gt; /μ&lt;sub&gt;VREF&lt;/sub&gt;) = 2.3% is obtained. This design&#039;s average line sensitivity (LS) is 0.072%/V (V&lt;sub&gt;dd&lt;/sub&gt; = 0.5V to 1.8V). However, the PSRR and LS values are temperature-dependent. At the high temperature of 130°C (worst-case), the PSRR and LS degrade to approximately -80.45 dB and 0.084 %/V, respectively.  The output noise at the frequency of 1 KHz is obtained as 167.34 nV/ √ Hz. The proposed VR occupies a small active area of 513.5 μm&lt;sup&gt;2&lt;/sup&gt;.</Abstract>
		<ObjectList>
			<Object Type="keyword">
			<Param Name="value">Voltage reference</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Temperature Coefficient</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Native transistor</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Line Sensitivity</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">Power supply ripple rejection</Param>
			</Object>
		</ObjectList>
<ArchiveCopySource DocType="pdf">https://eej.aut.ac.ir/article_5446_c79ec4f12a3564898baef75d49d910ae.pdf</ArchiveCopySource>
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