eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
1
10
10.22060/eej.2015.515
515
A Probabilistic Three-Phase Time Domain Electric Arc Furnace Model based on analytical method
M. Torabian Esfahani
1
B. Vahidi
2
PhD. Student, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran
Professor, Department of Electrical Engineering, Amirkabir University of Technology, Tehran, Iran
An electric arc furnace (EAF) is known as nonlinear and time variant load that causes power quality (PQ) problems such as, current, voltage and current harmonics, voltage flicker, frequency changes in power system. One of the most important problems to study the EAF behavior is the choice of a suitable model for this load. Hence, in this paper, a probabilistic three-phase model is proposed based on recovered hidden Markov model (RHMM) in time domain. To recover the HMM , the coupling factor is proposed. This factor estimates the past observations and considers the effects of all observations in different states. Regarding to the intense fluctuations of various parameters of EAF, this factor can improve the EAF model in different operating stages. This subject causes that the proposed model is closed to the actual model. To train the RHMM, actual measured samples are used. Likewise, different parameters of EAF' power system as, flexible cables, electrode, busbar are exactly considering to achieve an accurate model. Comparing the results of experimental and proposed model indicates the accuracy of the proposed model.
https://eej.aut.ac.ir/article_515_14d3ec449bc942f37e8f4f6979572336.pdf
Recovered Hidden Markov Model
Electric Arc Furnace
Voltage Flicker
Power Quality parameters
eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
11
16
10.22060/eej.2015.516
516
Improving the QoS in Intelligent Connected EVSE by Using RPL
M. Alishahi
1
M. H. Yaghmaee
2
G. Wu
3
Faculty Member, Department of Computer Engineering, Fariman Branch, Islamic Azad University, Fariman, Iran.
Professor, Department of Computer Engineering and Center of Excellence on Soft Computing and Intelligent Information Processing, Ferdowsi University of Mashhad, Mashhad, Iran.
Professor, Department of Electrical Engineering & Information Technology, Tohoku Gakuin University, Tagajo, Japan.
Nowadays, a great portion of researches research and industrial innovation is about the electric vehicles (EV) and also EV Supply Equipment (EVSE) that play an important role in this context. EVSE requires standardization via effective communication protocols. In this paper, we propose to customize the existing Internet standard Routing Protocol for Low Power and Lossy Networks (RPL) to facilitate the communication among networked EVSEs. RPL is a flexible protocol that has special specifications to support many low power and lossy nodes, which makes it self-healing and ideal to support the differing traffic activity in EVSE systems. Our idea to improve the Quality of Service (QoS) in this vehicular network is using classification of data type. Hence , we propose a Customized RPL which support supports classification and also two different Objective Functions (OF) that the simulation results shows show , effectively reduce the end to end delay for special kind of data packets. We study our proposed method under different scenarios to see how successful this idea is.
https://eej.aut.ac.ir/article_516_04dedd84c3ab8754c1cc4315b55da0ef.pdf
RPL
DODAG
QoS
EVSE
eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
17
22
10.22060/eej.2015.517
517
Automatic Discovery of Technology Networks for Industrial-Scale R&D IT Projects via Data Mining
S. Azimi
1
H. Veisi
2
R. Rahmani
3
Faculty Member, Department of New Sciences & Technology, Tehran University, Tehran, Iran
Assistant Professor, Department of New Sciences & Technology, Tehran University, Tehran, Iran
Assistant Professor, Department of New Sciences & Technology, Tehran University, Tehran, Iran
Industrial-Scale R&D IT Projects depend on many sub-technologies which need to be understood and have their risks analysed before the project can begin for their success. When planning such an industrial-scale project, the list of technologies and the associations of these technologies with each other is often complex and form a network. Discovery of this network of technologies is time consuming for a human to perform, due to the large number of technologies and due to the fact that the technologies are constantly changing. In this paper, a method is provided for the automatic discovery of the network of associations of Industrial IT technologies as a networked graph, using data mining and web-mining algorithms. The proposed process is an approach to form a dynamic weighted graph of technologies. A numeric value is calculated as similarity between technologies. A combination of data mining and web mining techniques have been used to achieve the results. The main objective is to invent a computerized reproducible method so that by the help of it, technological relation can be extracted and updated constantly. This method consists of six phases, of which four phases are performed automatically by novel algorithms introduced in this paper. The analysis of more than 8 million terms suggests that the proposed method provides acceptable results. This paper also provided recommendations to improve the suggested method.
https://eej.aut.ac.ir/article_517_ccfe7bf47894b4b403dd4eddea80745c.pdf
Technology Mining
Technology Graph
Data Mining
Text Mining
Similarity Algorithms
Web Robots
eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
23
29
10.22060/eej.2015.518
518
Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA
P. Soleimani Abhari
1
M. Dosaranian Moghadam
2
MSc. Student, Department of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
Assistant Professor, Department of Electrical, Biomedical and Mechatronics Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran
This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum operating frequency and higher maximum output frequency. Ripple Carry Adder (RCA) is used at each stage of Conventional pipeline accumulators, whereas the modified pipeline technique contains Carry Look-ahead Adder (CLA) instead of RCA. The proposed method consists of hierarchical adders that have three parts, two blocks of 4-bit CLA and a separated block to estimate carry bits independently. To reach a better frequency resolution in the DDFS, larger phase accumulator is needed. Moreover, in conventional DDFSs, as the number of phase bits increases, to have non-truncated phase mapping, huge amount of memory will be needed. The trigonometric relations of the sine and the cosine functions are used in the phase mapping technique proposed by Symon in order to reduce the size of the Look Up Table (LUT). The method applied in this work combines quarter wave symmetry of the sine samples, the phase difference between the sine and the cosine samples and trigonometric relations of the sine and the cosine functions to reduce the total memory size. The SFDR of the output wave will remain approximately constant (132 dBc) in comparison with the previous works. Finally, the proposed architecture is simulated on Stratix II FPGA. This structure has the frequency range of 0 to 245 MHz with 0.05 Hertz frequency resolution.
https://eej.aut.ac.ir/article_518_6d94f6bede50cd3e72e4eec489ea7cbc.pdf
DDFS
SFDR
Trigonometric identities
Phase mapping technique
Pipeline Accumulator
eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
31
37
10.22060/eej.2015.519
519
A Class E Power Amplifier with Low Voltage Stress
M. Hayati
1
S. Roshani
2
Professor, Department of Electrical Engineering, Faculty of Engineering, Razi University, Tagh-E-Bostan, Kermanshah-67149, Iran
Faculty Member, Department of Electrical Engineering, Kermanshah Branch, Islamic Azad University, Kermanshah, Iran
A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. The maximum switch voltage of the conventional class E PA is 3.56Vdc. However, higher switch voltage of about 4.5VDC may be occurred, by considering nonlinear drain-to-source capacitance in class E PA. The obtained peak switch voltage of the designed class E PA is approximately 75% of the conventional one with the same conditions, which shows a significant reduction in peak switch voltage. MOSFET parasitic nonlinear gate-to-drain and nonlinear drain-to-source capacitances of the MOSFET body junction diode also affect the switch voltage in class E PA, which are considered in this paper. The actual MOSFETs have these parasitic capacitances; therefore, it is necessary to consider these elements in the design procedure. Reduced switch voltage in class E PA relaxes the breakdown voltage constraints of the active device. In the switch voltage of the designed circuit, the zero voltage and zero derivative switching (ZVS and ZVDS) conditions are satisfied. Simulation of the presented circuit is performed using PSpice and LTspice softwares. For verification of the designed circuit, the presented PA is fabricated and measured.
https://eej.aut.ac.ir/article_519_dfb1cb08f32421702b3d35f7f9826ba3.pdf
Class E Power Amplifier
Low Voltage Stress
MOSFET Parasitic Capacitances
ZVS and ZVDS Conditions
eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
39
45
10.22060/eej.2015.520
520
Filtering Power Divider/Combiner Based on Half Mode Substrate Integrated Waveguide (HMSIW) Technology for High Power Applications
A. R. Moznebi
1
K. Afrooz
2
MSc Student, Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran
Assistant Professor, Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran
A filtering power divider/power combiner based on half mode substrate integrated waveguide technology for high power applications is proposed. This design includes one half mode substrate integrated waveguide cavity, one matched load, and four sections of quarter-wavelength transmission lines. The high isolation between output ports is obtained by combining the half mode substrate integrated waveguide cavity and microstrip network (one matched load and four sections of quarter-wavelength transmission lines). This structure utilizes for high power applications because of the matched load is connected to ground. The design is fabricated and tested by network analyzer. A good agreement between the simulated and measured results is observed. The measured results show that for a return loss of 15 dB, the bandwidth is from 5.15 to 5.35 GHz (IEEE 802.11a wireless local area network (WLAN) standard) and over this whole bandwidth, the output return loss and isolation between output ports are better than 14.5 dB and 17.5 dB, respectively. Also, the measured insertion loss is dB.
https://eej.aut.ac.ir/article_520_171e25d8b874c42211018ed8860777e9.pdf
Filtering Power Divider
Half Mode Substrate Integrated Waveguide (HMSIW)
Power Combiner
Power Divider
eng
Amirkabir University of Technology
AUT Journal of Electrical Engineering
2588-2910
2588-2929
2015-09-23
47
1
47
60
10.22060/eej.2015.521
521
Eigenvalue calculator for Islanded Inverter-Based Microgrids
A. Mahmoudi
1
S. H. Hosseinian
2
M. Kosari
3
The stability analysis of islanded inverter-based microgrids (IBMGs) is increasingly an important and challenging topic due to the nonlinearity of IBMGs. In this paper, a new linear model for such microgrids as well as an iterative method to correct the linear model is proposed. Using the linear model makes it easy to analyze the eigenvalues and stability of IBMGs due to the fact that it derives the eigenvalues directly and the linearization around an operating point to study the small signal stability and also use the newton-raphson method or other load flow solutions to solve these systems are no longer needed. An effective eigenvalue calculator is developed which is able to calculate the eigenvalues of IBMGs in the first few iterations of the proposed method. The proposed method provides the superior performance considering the simulation time compared to the conventional methods. The validation and comparison of the results show the performance of the proposed method.
https://eej.aut.ac.ir/article_521_58ae4984fb950c9c5d8bf758e2815ea5.pdf
Inverter-based microgrids
Stability Analysis
Eigenvalue calculator
Linear models
State-space model